1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a CMOS static RAM.
2. Description of the Background Art
FIG. 15 is a circuit diagram showing an exemplary memory cell (memory circuit) of multiport memory in the background art, e.g., disclosed in Japanese Patent Publication No. 58-27917 (FIG. 4).
As shown in FIG. 15, PMOS transistors PI1 and PI2 and NMOS transistors NI1 and NI2 constitute a memory cell storage unit 9. Sources of the PMOS transistors PI1 and PI2 are connected to a power supply VDD, and sources of the NMOS transistors NI1 and NI2 are connected to a ground potential GND. Drains of the PMOS transistor PI1 and the NMOS transistor NIl and gates of the PMOS transistor PI2 and the NMOS transistor NI2 are commonly connected to a memory terminal 21, and drains of the PMOS transistor PI2 and the NMOS transistor NI2 and gates of the PMOS transistor PI1 and the NMOS transistor NI1 are commonly connected to a memory terminal 22.
Specifically, a first CMOS inverter consisting of the PMOS transistor PI1 and the NMOS transistor NI1 and a second CMOS inverter consisting of the PMOS transistor PI2 and the NMOS transistor NI2 are cross-connected, to form the memory cell storage unit 9.
A drain of an access (NMOS) transistor NA1 is connected to the memory terminal 21. A bit line BL1 is connected to a source of an access transistor N1 and a word line WL1 is connected to a gate thereof. A drain of an access (NMOS) transistor NA2 is connected to the memory terminal 22. A bit line BL2 is connected to a source of an access transistor N2 and a word line WL2 is connected to a gate thereof.
Further, gates of NMOS transistors N21 and N22 are connected to the memory terminals 21 and 22, respectively, and sources thereof are commonly connected the ground potential GND. Sources of NMOS transistors N23 and N24 are connected to drains of the NMOS transistors N21 and N22, respectively. A read word line RWL1 and a read bit line RBL1 are connected to a gate and a drain of the NMOS transistor N23, respectively, and a read word line RWL2 and a read bit line RBL2 are connected to a gate and a drain of the NMOS transistor N24, respectively.
With respect to this structure, an operation of the memory cell storage unit 9 of multiport memory in the background art shown in FIG. 15 will be discussed. The memory terminals 21 and 22 have a complementary relation, and for example, when the memory terminal 21 is in a logical xe2x80x9cHxe2x80x9d state, the memory terminal 22 comes into a logical xe2x80x9cLxe2x80x9d state, being stable. Conversely, when the memory terminal 21 is in the logical xe2x80x9cLxe2x80x9d state, the memory terminal 22 comes into the logical xe2x80x9cHxe2x80x9d state, being stable. Thus, this structure can hold stored data of the two stable states, depending on whether the states of the memory terminals 21 and 22 are xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d.
If the memory terminal 21 is stable in the logical xe2x80x9cHxe2x80x9d state (in other words, the memory terminal 22 is in the logical xe2x80x9cLxe2x80x9d state), the PMOS transistor pI1 is in an ON state and the PMOS transistor PI2 is in an OFF state. Further, the NMOS transistor NI1 is in the OFF state and the NMOS transistor NI2 is in the ON state.
Next, a read/write operation using the word line WL1 (WL2) and the bit line BL1 (BL2) will be discussed. When the word line WL1 is in the xe2x80x9cLxe2x80x9d state, the transistor NA1 is in the OFF state, and the memory terminal 21 is electrically cut off with the bit line BL1 which corresponds to a read/write terminal for data. In other words, the stored data is held. When the word line WL1 is brought into the xe2x80x9cHxe2x80x9d state from the xe2x80x9cLxe2x80x9d state in response to an external signal, the transistor NA1 comes into the ON state from the OFF state and the memory terminal 21 electrically gets connected to the bit line BL1.
In this case, if the bit line BL1 is not externally driven, the data of the memory terminal 21 is propagated to the bit line BL1 through the transistor NA1 and read out. Thus performed is a read operation in the read/write operation.
On the other hand, when the word line WL1 is in the xe2x80x9cHxe2x80x9d state, if the bit line BL1 is strongly driven into the xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d state by a not-shown external circuit, the data of the bit line BL1 which is driven is propagated to the memory terminal 21 through the transistor NA1 and data of the memory terminal 21 is rewritten by the data of the bit line BL1. Thus performed is a write operation in the read/write operation.
When the word line WL1 is returned to the xe2x80x9cLxe2x80x9d state from the xe2x80x9cHxe2x80x9d state by an external signal, the memory terminal 21 comes into a hold-mode again. An operation of a port on the side of the transistor NA2 connected to the memory terminal 22 is the same as the above operation and therefore not discussed herein.
Next, a read operation using the read word line RWL1 (RWL2) and the read bit line RBL1 (RBL2) will be discussed. When the read word line RWL1 is in the xe2x80x9cLxe2x80x9d state, the NMOS transistor N23 is in the OFF state, and a read terminal m1 is electrically cut off with the read bit line RBL1. In an initial state, the read bit line RBL1 is precharged in the xe2x80x9cHxe2x80x9d state by a not-shown precharge circuit.
When the read word line RWL1 is brought into the xe2x80x9cHxe2x80x9d state from the xe2x80x9cLxe2x80x9d state in response to an external signal, the NMOS transistor N23 comes into the ON state from the OFF state and the memory terminal m1 electrically gets connected to the read bit line RBL1. If the hold-mode of the memory terminal 21 is xe2x80x9cHxe2x80x9d, the NMOS transistor N21 is in the ON state and the read bit line RBL1 electrically gets connected to the ground potential GND through the NMOS transistors N23 and N21. Therefore, the read bit line RBL1 is brought into the xe2x80x9cLxe2x80x9d state from the xe2x80x9cHxe2x80x9d state and data of xe2x80x9cLxe2x80x9d which is inverted data of the memory terminal 21 is read out.
Conversely, if the hold-mode of the memory terminal 21 is xe2x80x9cLxe2x80x9d, the NMOS transistor N21 is in the OFF state and the read bit line RBL1 is electrically cut off with the ground potential GND. Therefore, the read bit line RBL1 remains the xe2x80x9cHxe2x80x9d state and data of xe2x80x9cHxe2x80x9d which is inverted data of the memory terminal 21 is read out. When the read word line RWL1 is returned to the xe2x80x9cLxe2x80x9d state from the xe2x80x9cHxe2x80x9d state by an external signal, the memory terminal m1 gets cut off with the read bit line RBL1 again and the read bit line RBL1 is precharged into the xe2x80x9cHxe2x80x9d state again for the next read operation. Further, the read bit line RBL1 and the memory terminal 21 are not electrically connected to each other and no write operation is performed by the NMOS transistor N23. A read operation of a port on the side of the NMOS transistor N24 connected to another memory terminal m2 is the same as the above operation and therefore not discussed.
As discussed above, the memory cell including the memory cell storage unit 9 of multiport memory in the background art shown in FIG. 15 has a structure comprising two ports for reading and writing and two ports for only reading. FIG. 15 shows a four-port memory cell consisting of totally ten MOS transistors, i.e., eight NMOS transistors and two PMOS transistors.
The four-port memory cell is constituted of ten transistors as shown in FIG. 15, and in the structure of a multiport memory cell, like this example, the number of transistors constituting the multiport memory cell increases depending on the number of ports and this disadvantageously results in enlargement of cell area.
The present invention is directed to a semiconductor memory device. According to a first aspect of the present invention, the semiconductor memory device has a memory cell storage unit for data storage formed in a semiconductor substrate. The memory cell storage unit of the first aspect comprises first and second MIS transistors both of a first conductivity type, one electrode of the first MIS transistor and one electrode of the second MIS transistor being commonly connected to a first power supply, the other electrode of the first MIS transistor and the other electrode of the second MIS transistor serving as first and second memory terminals, respectively, the first and second memory terminals being connected to control electrodes of the second and first MIS transistors, respectively, and the first and second memory terminals each being set to a first power supply judged-potential that can be judged as a potential on the side of the first power supply when the first and second MIS transistors are in an ON state, and the memory cell storage unit of the first aspect further comprises third and fourth MIS transistors both of a second conductivity type, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor being connected to each other, control electrodes of the third and fourth MIS transistors being connected to the first and second memory terminals, respectively, the other electrode of the third MIS transistor and the other electrode of the fourth MIS transistor being independent of the first and second memory terminals, and backgate terminals of the third and fourth MIS transistors for setting a substrate potential being connected to a second power supply, and in the semiconductor memory device of the first aspect, the first to fourth MIS transistors are provided so that a potential of the first memory terminal is stable at a second power supply judged-potential that can be judged as a potential on the side of the second power supply when the first MIS transistor is in an OFF state and a potential of the second memory terminal is stable at the second power supply judged-potential when the second MIS transistor is in the OFF state.
According to a second aspect of the present invention, the semiconductor memory device has a memory cell storage unit for data storage formed in a semiconductor substrate. The memory cell storage unit of the second aspect comprises first and second MIS transistors both of a first conductivity type, one electrode of the first MIS transistor and one electrode of the second MIS transistor being commonly connected to a first power supply, the other electrode of the first MIS transistor and the other electrode of the second MIS transistor serving as first and second memory terminals, respectively, the first and second memory terminals being connected to control electrodes of the second and first MIS transistors, respectively, and the first and second memory terminals each being set to a first power supply judged-potential that can be judged as a potential on the side of the first power supply when the first and second MIS transistors are in an ON state, and the memory cell storage unit of the second aspect further comprises third and fourth MIS transistors both of a second conductivity type, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor not being fixed to any potential, control electrodes of the third and fourth MIS transistors being connected to the first and second memory terminals, respectively, the other electrode of the third MIS transistor and the other electrode of the fourth MIS transistor being connected to the second and first memory terminals, and backgate terminals of the third and fourth MIS transistors for setting a substrate potential being connected to a second power supply, and in the semiconductor memory device of the second aspect, the first to fourth MIS transistors are provided so that a potential of the first memory terminal is stable at a second power supply judged-potential that can be judged as a potential on the side of the second power supply when the first MIS transistor is in an OFF state and a potential of the second memory terminal is stable at the second power supply judged-potential when the second MIS transistor is in the OFF state.
According to a third aspect of the present invention, in the semiconductor memory device of the first aspect, assuming that currents flowing between one electrode and the other electrode of the first MIS transistor in the OFF state are first off-leak currents, currents flowing between one electrode and the other electrode of the second MIS transistor in the OFF state are second off-leak currents, currents flowing between the control electrode of the first MIS transistor and the semiconductor substrate are first gate-leak currents, currents flowing between the control electrode of the second MIS transistor and the semiconductor substrate are second gate-leak currents, currents flowing between the control electrode of the third MIS transistor and the semiconductor substrate are third gate-leak currents and currents flowing between the control electrode of the fourth MIS transistor and the semiconductor substrate are fourth gate-leak currents, the first to fourth MIS transistors are provided so that the amount of the third gate-leak currents is not less than the total amount of the first off-leak currents and the second gate-leak currents during a period until at least the potential of the first memory terminal becomes the second power supply judged-potential and the amount of the fourth gate-leak currents is not less than the total amount of the second off-leak currents and the first gate-leak currents during a period until at least the potential of the second memory terminal becomes the second power supply judged-potential.
According to a fourth aspect of the present invention, in the semiconductor memory device of the first aspect, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are set to a fixed potential.
According to a fifth aspect of the present invention, the semiconductor memory device of the first aspect further comprises a first access transistor having one electrode connected to an access memory terminal which is one of the first and second memory terminals, the other electrode connected to a write/read line and a control electrode connected to a write/read control line.
According to a sixth aspect of the present invention, in the semiconductor memory device of the fifth aspect, the write/read line includes first and second write/read lines, and the first access transistor includes a fifth MIS transistor having one electrode connected to the first memory terminal and the other electrode connected to the first write/read line; and a sixth MIS transistor having one electrode connected to the second memory terminal and the other electrode connected to the second write/read line.
According to a seventh aspect of the present invention, in the semiconductor memory device of the sixth aspect, the write/read control line includes first and second write/read control lines, the fifth MIS transistor has a control electrode connected to the first write/read control line, and the sixth MIS transistor has a control electrode connected to the second write/read control line.
According to an eighth aspect of the present invention, in the semiconductor memory device of the fourth aspect, the third and fourth MIS transistors include a MIS transistor which turns on/off when the potentials of the first and second memory terminals are the first/second power supply judged-potentials, respectively, and the other electrodes of the third and fourth MIS transistors are defined as first and second read terminals, respectively, and the semiconductor memory device of the eighth aspect further comprises: a second access transistor having one electrode connected to an access read terminal which is one of the first and second read terminals, the other electrode connected to a read only line and a control electrode connected to a read only control line.
According to a ninth aspect of the present invention, in the semiconductor memory device of the eighth aspect, the read only line includes first and second read only lines, and the second access transistor includes a seventh MIS transistor having one electrode connected to the first read terminal and the other electrode connected to the first read only line; and an eighth MIS transistor having one electrode connected to the second read terminal and the other electrode connected to the second read only line.
According to a tenth aspect of the present invention, in the semiconductor memory device of the ninth aspect, the read only control line includes first and second read only control lines, the seventh MIS transistor has a control electrode connected to the first read only control line, and the eighth MIS transistor has a control electrode connected to the second read only control line.
According to an eleventh aspect of the present invention, in the semiconductor memory device of the fourth aspect, the other electrodes of the third and fourth MIS transistors are defined as first and second read terminals, respectively, and the semiconductor memory device of the eleventh aspect further comprises: a seventh MIS transistor having one electrode connected to the first read terminal, the other electrode connected to a comparison judgment line and a control electrode connected to a first comparison judgment control line; and an eighth MIS transistor having one electrode connected to the second read terminal, the other electrode connected to the comparison judgment line and a control electrode connected to a second comparison judgment control line.
According to a twelfth aspect of the present invention, the semiconductor memory device of the first aspect further comprises: a seventh MIS transistor having one electrode connected to a comparison judgment line, the other electrode set to a fixed potential and a control electrode connected to one electrode of the third MIS transistor and one electrode of the fourth MIS transistor; and first and second comparison judgment control lines connected to the other electrodes of the third and fourth MIS transistors, respectively.
Preferably, in the semiconductor memory device of the fourth aspect, the fixed potential includes a potential of one of the first and second power supplies.
Preferably, in the semiconductor memory device of the first aspect, the first conductivity type includes a P-type conductivity, the second conductivity type includes an N-type conductivity, and a potential of the first power supply is higher than that of the second power supply.
Preferably, in the semiconductor memory device of the first aspect, the first conductivity type includes an N-type conductivity, the second conductivity type includes a P-type conductivity, and a potential of the first power supply is lower than that of the second power supply.
Preferably, in the semiconductor memory device of the second aspect, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are connected to each other.
Preferably, in the semiconductor memory device of the second aspect, one electrode and the other electrode of the third MIS transistor are connected to each other, and one electrode and the other electrode of the fourth MIS transistor are connected to each other.
Preferably, in the semiconductor memory device of the second aspect, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are in a floating state.
Preferably, in the semiconductor memory device of the second aspect, the first conductivity type includes a P-type conductivity, the second conductivity type includes an N-type conductivity, and a potential of the first power supply is higher than that of the second power supply.
Preferably, in The semiconductor memory device of the second aspect, the first conductivity type includes an N-type conductivity, the second conductivity type includes a P-type conductivity, and a potential of the first power supply is lower than that of the second power supply.
In the semiconductor memory device of the first aspect of the present invention, the first to fourth MIS transistors are provided so that the potential of the first memory terminal can be stable at the second power supply judged-potential when the first MIS transistor is in the OFF state and the potential of the second memory terminal can be stable at the second power supply judged-potential when the second MIS transistor is in the OFF state.
Accordingly, when either one of the first and second MIS transistors is made the ON state and the other is made the OFF state, one of the first and second memory terminals is set to the first power supply judged-potential through the first or second MIS transistor which is in the ON state and the other is set to the second power supply judged-potential as discussed above, whereby information storage is performed between the first and second memory terminals.
As a result, since the memory cell storage unit needs a cross connection of only the first and second MIS transistors and that allows a simple layout, a semiconductor memory device having a memory cell structure to ensure reduction in cell area can be provided.
According to the second aspect of the present invention, a semiconductor memory device having a memory cell structure which ensures reduction in cell area, like that of the first aspect, can be achieved.
Further, since the other electrodes of the third and fourth MIS transistors are connected to the second and first memory terminals, respectively, it is possible to improve the soft-error resistance by addition of capacitance between the other electrodes and the control electrodes of the third and fourth MIS transistors to the second and first memory terminals.
In the semiconductor memory device of the third aspect of the present invention, by providing the third and fourth MIS transistors so that the third and fourth gate-leak currents can satisfy the above condition, the potentials of the first and second memory terminals are always set to the second power supply judged-potential when the first and second MIS transistors are in the OFF state, whereby information storage can be performed between the first and second memory terminals.
In the semiconductor memory device of the fourth aspect of the present invention, if the third and fourth MIS transistors are set to turn on/off when the potentials of the first and second memory terminals are set to the first/second power supply judged-potential by setting one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are set to fixed potentials, the stored content in the memory cell storage unit can be read out by utilizing whether the potential obtained by the other electrodes of the third and fourth MIS transistors are fixed potentials or not.
The semiconductor memory device of the fifth aspect of the present invention can perform a write operation by turning on the first access transistor by the write/read control line to set the potential of the access memory terminal while setting the potential of the write/read line and a read operation by turning on the first access transistor by the write/read control line to read the potential of the access memory terminal out to the write/read line.
The semiconductor memory device of the sixth aspect of the present invention can perform write/read operations on the respective two ports by utilizing the fifth and sixth MIS transistors. Further, a write operation is performed by setting such data on the first and second write/read lines as to have a complementary relation and a read operation is performed on the basis of the potential difference between the first and second write/read lines, and therefore a stable write/read operation can be achieved.
The semiconductor memory device of the seventh aspect of the present invention can perform write/read operations independent of each other on the respective two ports by the first and second write/read control lines.
In the semiconductor memory device of the eighth aspect of the present invention, since the potential of the read only line is set to a potential different from the fixed potential and thereafter the second access transistor is turned on by the read only line, a read operation can be performed on the basis of whether the potential of the read only line is the fixed potential or not.
The semiconductor memory device of the ninth aspect of the present invention can perform write/read operations on the respective two ports by utilizing the seventh and eighth MIS transistors. Further, a read operation is performed on the basis of the potential difference between the first and second read only lines. Therefore, a stable read operation can be achieved.
The semiconductor memory device of the tenth aspect of the present invention can perform write/read operations independent of each other on the respective two ports by the first and second read only control lines.
In the semiconductor memory device of the eleventh aspect of the present invention, since the potential of the comparison judgment line is set to a potential different from the fixed potential and thereafter one of the seventh and eighth MIS transistors is made the ON state and the other is made the OFF state by the first and second comparison judgment control lines, a comparison operation for checking if the data- stored in the memory cell storage unit and the search data match each other on the basis of whether the potential of the comparison judgment line is the fixed potential or not.
In the semiconductor memory device of the twelfth aspect of the present invention, since the potential of the comparison judgment line is set to a potential different from the fixed potential and thereafter one of the first and second comparison judgment control lines and the other are set to the potentials to turn on and off the seventh MIS transistor, respectively, a comparison operation for checking if the data stored in the memory cell storage unit and the search data match each other on the basis of whether the potential of the comparison judgment line is the fixed potential or not.
An object of the present invention is to provide a semiconductor memory device having a memory cell structure which ensures reduction in cell area.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.